1. Field of the Invention
This invention relates to Dynamic Random Access Memories, DRAMs, and more particularly to the prevention of data loss in DRAMs using Extended Data Out (EDO) mode. The invention provides a logic circuit which produces an address lock output and a data latch output. The address lock output is fed to an address input buffer and the data latch output is fed to a data output buffer. The address input buffer is locked and the data output buffer is latched until the data is established.
2. Description of Related Art
When the Extended Data Out (EDO) mode is used in Dynamic Random Access Memory arrays the page mode cycle time is reduced with the same data out cycle time. This can cause loss of data if the data is not fully established before the time window allocated to reading out the data is closed. This invention provides a self-timed address locking and data latching circuit to protect the data during readout.